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IN16C554A quadruple uart february 2009 rev 1.01 1 1. description IN16C554A is an enhanced quadruple version of the 16c550uart (universal asynchronous receiver transmitter). IN16C554A is in part an upgrade version of in16c554, as it is designed for 3.3v only and has auto-cts, auto-rts functions. in IN16C554A, each channel can be put into fifo mode to relieve the cpu of excessive software overhead. in this mode, internal fi fos are activated and 16 bytes plus 3 bit of error data per byte can be stored in both receive and transmit modes. each channel performs serial-to-parallel c onversion on data characters received from a peripheral device or a modem, and parallel-t o-serial conversion on data characters received from the cpu. the cpu can read the complete status of the uart at any time during the functional operation. the status information includes the type and condition of the transfer operations being performed by t he uart, as well as any error conditions such as parity, overrun, framing, and break interrupt. IN16C554A includes a programmable baud rate generator which is capable of dividing the timing reference clock input by divisors of 1 to 2 16 -1, and producing a 16x clock for driving the internal transmitter logic. provisions are also included to use this clock to drive the receiver logic.IN16C554A has complete modem-control capability and an interrupt system that can be programmed to the user?s requirements, minimizing the computing required to handle the communication links. moreover IN16C554A can select hardware flow control. hardware flow control significantly reduces software overhead and increases system efficiency. 2. features in the fifo mode, each channel?s transmitter and receiver is buffered with 16-byte fifo to reduce the number of interrupts to cpu. adds or deletes standard asynchronous communi cation bits (start, stop, parity) to or from the serial data. holding register and shift register elim inate need for precise synchronization between the cpu and serial data. independently controlled transmit, receiv e, line status and data interrupts. programmable baud rate generators which al low division of any input reference clock by 1 to 2 16 -1 and generate an internal 16x clock. independent receiver clock input modem control functions (cts#, rts#, dsr#, dtr#, ri#, and dcd#). fully programmable serial interface characteristics. - 5-, 6-, 7-, or 8-bit characters - even-, odd-, or no-parity bit 1-, 1.5-, 2-stop bit generation. ( like other general uarts, in16c554 checks only one stop bit, no matter how many they are)
IN16C554A quad uart july 2008 rev 0.99 2 false start bit detection generates or detects line break internal diagnostic capabilities : loopbac k controls for communications link fault isolation. full prioritized interrupt system controls hardware (rts#/cts#) flow control 3. ordering information table 1: ordering information part number package operating temperature range device status IN16C554A-tq80 80-pin tqfp -20 to +85 active IN16C554A-pl68 68-pin plcc -20 to +85 active IN16C554A-tq64 64-pin tqfp -20 to +85 active
IN16C554A quadruple uart february 2009 rev 1.01 3 4. block diagram figure 1: block diagram cs#[3:0] flow uart 0 baud rate txd2 fifo shift control cts1#/dsr1#/dcd1#/ri1# fifo logic rxd1 register signal control rxd3 uart 1 register control control transmit shift rxd2 ior#/iow# cts3#/dsr3#/dcd3#/ri3# control reset register logic register rts0#/dtr0# rts2#/dtr2# txd3 cts2#/dsr2#/dcd2#/ri2# xta l 1 transmit hardware hardware generator rxd0 register uart 2 xta l 2 control data and txd0 a[2:0] mod em rts3#/dtr3# uart 3 cts0#/dsr0#/dcd0#/ri0# sb16c554a d[7:0] int[3:0] rts1#/dtr1# interrupt flow logic txd1 receive logic receive logic txrdy#/rxrdy# logic clock and
IN16C554A quad uart july 2008 rev 0.99 4 5. pin configuration 5.1 pin configuration for 80-pin tqfp package figure 2: 80-pin tqfp pin configuration 11 reset 75 sb16c554a-tq80 34 51 a0 nc 76 nior 63 d1 41 nrts1 d7 int0 ndtr3 nri1 nc 26 int2 txd2 28 ncts2 73 44 ndsr3 78 14 gnd nc - no internal connection a1 niow 47 ndtr1 38 txd1 64 5 68 40 1 72 49 59 18 77 55 43 52 80 79 nri2 nc int3 35 ndcd2 62 nrts0 61 46 ncs0 ndsr1 xtal2 vcc ncts1 d6 22 4 74 d0 nc 619 17 d4 gnd 32 nc ndtr0 71 16 24 d5 vcc 54 nri0 nc 53 8 56 nc ncs1 30 xtal1 gnd rxd2 nrts2 20 12 23 nrts3 nrxrdy 29 3 15 ncts3 10 ndcd1 a2 txd3 70 int1 39 50 29 37 nc 36 nc ncs3 66 nri3 33 7 60 nc ncts0 nc 13 nc rxd0 ndcd3 ndtr2 57 65 ntxrdy ncs2 58 rxd1 d3 69 31 d2 25 ndcd0 21 ndsr0 gnd 27 nintn 48 vcc txd0 67 42 vcc rxd3 45 nc ndsr2
IN16C554A quadruple uart february 2009 rev 1.01 5 5.2 pin configuration for 68-pin plcc package figure 3: 68-pin plcc pin configuration nrts3 17 34 15 4 vcc ndcd3 64 nc 60 13 2 ndsr2 ndcd1 d7 d6 gnd 32 rxd0 35 d1 gnd 22 ncs1 rxd1 14 ncts2 ndtr0 d2 a1 ncts1 txd1 21 ntxrdy 42 19 niow 45 ndtr1 30 nintn 6 gnd gnd 24 11 59 rxd2 52 67 766 57 51 nior 50 ndsr3 61 ncts3 3 int0 vcc 1 nri1 ncs2 16 23 36 43 nri3 d5 18 ncs0 reset 12 nrts2 ncts0 54 vcc 9 26 rxd3 46 40 33 8 nri0 55 ndcd0 ndsr0 txd2 sb16c554a-pl68 int2 nrts1 a0 nrxrdy 58 20 vcc d0 62 ndtr2 38 xtal2 d3 29 37 25 41 int1 44 47 56 48 27 txd0 63 a2 65 ndcd2 ndsr1 txd3 10 nri2 int3 53 28 31 ndtr3 ncs3 5 nrts0 68 49 xtal1 d4 39
IN16C554A quad uart july 2008 rev 0.99 6 5.2 pin configuration for 64-pin-tqfp package figure 4: 64-pin tqfp pin configuration 39 62 45 d0 d6 7 vcc 24 rxd3 ndtr3 12 gnd txd0 28 36 ncs1 59 ndcd3 4 a0 38 60 52 nri0 nrts1 61 43 a1 nri3 49 16 21 3 30 gnd 50 d7 17 nintn ndsr2 63 22 47 vcc 19 int2 niow 58 23 25 nior 53 26 20 8 rxd0 txd1 33 ndtr1 42 nrts3 sb16c554a-tq64 rxd2 40 41 ncts1 ncs2 18 6 2 int1 nri2 xtal2 51 d5 ncts0 gnd int3 ndcd2 54 35 d2 1 ncts2 nrts2 txd2 ndsr0 gnd 29 14 56 64 ncs3 ndsr1 ncts3 13 9 48 d4 ndtr2 rxd1 reset a2 ndtr0 xtal1 ncs0 d3 nri1 55 10 int0 34 5 11 nrts0 ndsr3 vcc 15 32 57 31 27 37 d1 ndcd1 ndcd0 46 txd3 44
IN16C554A quadruple uart february 2009 rev 1.01 7 5.3 pin description table 2: pin description data bus interface name pin type description tqfp80 plcc68 tqfp64 a0 a1 a2 48 47 46 34 33 32 24 23 22 i i i address bus lines [2:0]. these 3 address lines select one of the internal registers in uart channel 0-3 during a data bus transaction. d0 d1 d2 d3 d4 d5 d6 d7 7 8 9 11 12 13 14 15 66 67 68 1 2 3 4 5 53 54 55 56 57 58 59 60 i/o i/o i/o i/o i/o i/o i/o i/o data bus lines [7:0]. these pins are tri-state data bus for data transfer to or from the controlling cpu. ior# 70 52 40 i read data (active low strobe). a valid low level on ior# will load the data of an internal register defined by address lines a [2:0] onto the uart data bus for access by an external cpu. iow# 31 18 9 i write data (active low strobe). a valid low level on iow# will transfer the data from external cpu to an internal register that is defined by address lines a [2:0]. cs0# cs1# cs2# cs3# 28 33 68 73 16 20 50 54 7 11 38 42 i i i i chip select 0, 1, 2, and 3 (active low). these pins enable data transfers between the external cpu and the uart for the respective channel. int0/gint int1 int2 int3 27 34 67 74 15 21 49 55 6 12 37 43 o o o o external interrupt output. when activated, intx output informs cpu that uart has an interrupt to be serviced. intsel 6 65 52 i interrupt select. when intsel is left open or low state, the tri-state interrupts available on int0-3 are enabled by mcr[3]. but, when intsel is in high state, int0-3 are always enabled. txrdy# 55 39 o transmitter ready (active low). this is asserted by tx fifo/thr status for transmit channels 0-3. rxrdy# 54 38 o receiver ready (active low). this is asserted by rx fifo/rhr status for receive channels 0-3.
IN16C554A quad uart july 2008 rev 0.99 8 table 2: pin description? continued modem and serial i/o interface name pin type description tqfp80 plcc68 tqfp64 txd0 txd1 txd2 txd3 29 32 69 72 17 19 51 53 8 10 39 41 o o o o transmit data. these pins are individual transmit data output. during the local loop-back mode, the txd output pin is disabled and txd data is internally connected to the rxd input. rxd0 rxd1 rxd2 rxd3 17 44 57 4 7 29 41 63 62 20 29 51 i i i i receive data. these pins are individual receive data input. during the local loop-back mode, the rxd input pin is disabled and rxd data is internally connected to the txd output. rts0# rts1# rts2# rts3# 26 35 66 75 14 22 48 56 5 13 36 44 o o o o request to send (active low). these pins indicate that the uart is ready to send data to the modem, and affect transmit and receive operations only when auto-rts function is enabled. cts0# cts1# cts2# cts3# 23 38 63 78 11 25 45 59 2 16 33 47 i i i i clear to send (active low). these pins indicate the modem is ready to accept transmitted data from the uart, and affect transmit and receive operations only when auto-cts function is enabled. dtr0# dtr1# dtr2# dtr3# 24 37 64 77 12 24 46 58 3 15 34 46 o o o o data terminal ready (active low). these pins indicate uart is ready to transmit or receive data. dsr0# dsr1# dsr2# dsr3# 22 39 62 79 10 26 44 60 1 17 32 48 i i i i data set ready (active low). these pins indicate modem is powered-on and is ready for data exchange with uart. dcd0# dcd1# dcd2# dcd3# 19 42 59 2 9 27 43 61 64 18 31 49 i i i i carrier detect (active low). these pins indicate that a carrier has been detected by modem. ri0# ri1# ri2# ri3# 18 43 58 3 8 28 42 62 63 19 30 50 i i i i ring indicator (active low). these pins indicate the modem has received a ringing signal from telephone line. a low to high transition on these input pins generates a modem status interrupt, if enabled. other interfaces name pin type description tqfp80 plcc68 tqfp64 xtal1 50 35 25 i crystal or external clock input. xtal2 51 36 26 o crystal or buffered clock output.
IN16C554A quadruple uart february 2009 rev 1.01 9 table 2: pin description? continued other interfaces name pin type description tqfp80 plcc68 tqfp64 reset 53 37 27 i reset (active high). this pin will reset the internal registers and all the outputs. vcc 5 25 45 65 13 30 47 64 4 21 35 i power supply input. 3.3v (2.7v ~ 3.6v) gnd 16 36 56 76 6, 23 40 57 14 28 45 61 i signal and power ground. nc 1 10 20 21 30 40 41 49 52 60 61 71 80 31 - no internal connection.
IN16C554A quad uart july 2008 rev 0.99 10 6. functional description the IN16C554A uart is pin-to-pin compatible with the tl16c554a and sb16c554 uarts. the IN16C554A has same function with in16c554 except for flow control and voltage that are used in operations. IN16C554A can select hardware flow control. hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the rts# output and cts# input signals. 6.1 hardware flow control hardware flow control is executed by auto-rts and auto-cts. auto-rts and auto-cts can be enabled/disabled by programming mcr [5]. if auto-rts is enabled, it reports that it cannot receive more data by asserting rts# when rx fifo has no space. then after the data stored in rx fifo is read by cpu, it reports that it can receive new data by deasseting rts# when the amount of existing data in rx fifo is less than trigger level. when auto-cts is enabled and cts# is cleared to ?0?, transmitting data to tx fifo has to be suspended because external device has r eported that it cannot accept more data. when data transmission has been suspended and cts# is set to ?1?, data in tx fifo is retransmitted because external device has repor ted that it can accept more data. these operations prevent overrun during communication and if hardware flow control is disabled and transmit data rate exceeds rx fifo service latency, overrun error occurs. 6.1.1 auto-rts to enable auto-rts, msr [5], [1] should be set to ?1?. once enabled, rts# outputs ?0?. if the number of received data in rx fifo reaches a trigger level, rts# will be changed to ?1? and if not, holds ?0?. this state indicates that rx fifo can accept more data. after rts# changed to ?1? and reported to the cpu that it cannot accept more data, the cpu reads the data in rx fifo and then the amo unt of data in rx fifo reduces. when the amount of data in rx fifo has a space to store data, rts# changes to ?0? and reports that it can accept more data. that is, if rts# is ?0? now, rts# is not changed to ?1? until the amount in rx fifo reaches to trigger le vel. but if rts# is ?1? now, rts# is not changed to ?0? until the rx fifo has at least one available byte space. while auto-rts is enabled, you can verify if rts# is ?0? or ?1? by fsr[5]. if fsr[5] is ?0?, rts# is ?0? and if ?1?, rts# is ?1?, too. when ier[6] is set to ?1? and rts# is changed from ?0? to ?1? by auto-rts function, interrupt o ccurs and it is displayed on isr[5:0]. interrupts by auto-rts function are removed if msr is read. rts# is changed from ?0? to ?1? after the first stop bit is received. figure 5 shows the rts# timing chart while auto-rts is enabled. in figure 5, data byte n-1 is received a nd rts# is deasserted when the amount of data in rx fifo is larger than the value wri tten in fur. uart completes transmitting new data (data byte n) which has started being transmitted even though external uart recognizes rts# has been deasserted. after that, the device stops transmitting more data.
IN16C554A quadruple uart february 2009 rev 1.01 11 figure 5: rts# functional timing 6.1.2 auto-cts setting msr [5] to ?1? enables auto-rts. if enab led, data in tx fifo are determined to be transmitted or suspended by the value of cts#. if ?0?, it means external uart can receive new data and data in tx fifo are transmitted through txd pin. if ?1?, it means external uart can not accept more data a nd data in tx fifo are not transmitted. but data being transmitted by then complete transmission. these procedures are performed irrespective of fifo modes. while auto-cts is enabled, you can verify the input value of cts# by fsr[1]. if ?0?, cts# is ?0? and it means external uart can accept new data, if ?1?, cts# is ?1? and it means external ua rt can not accept more data and data in tx fifo are not being transmitted. if ier[7] is se t to ?1?, interrupt is generated by auto-cts when the input of cts# is changed from ?0? to ?1?, and it is shown on isr[5:0]. interrupts generated by auto-cts are removed if msr is read. 6.2 programmable baud rate generator the IN16C554A has a programmable baud rate generator. the baud rate generator divides this clock frequency by a programmable divisor (dll and dlm) between 1 and (2 16 ? 1) to obtain a 16x sampling rate clock of the serial data rate. the sampling rate clock is used by transmitter for data bit shifting and receiver for data sampling. the divisor of the baud rate generator is: divisor = ( xtal1 crystal input frequency ) (desired baud rate x 16) figure 6: baud rate generator block diagram progammable divisor internal xta l 1 baud rate oscillator xta l 2 internal baud rate clock for tra nsmitter and receiver generator logic logic da ta by te n da ta by te 1 stop ior# start da ta by te n start rts# da ta by te 2 stop start da ta by te n- 1 rxd
IN16C554A quad uart july 2008 rev 0.99 12 dll and dlm must be written to in order to program the baud rate. dll and dlm are the least and most significant byte of the baud rate divisor, respectively. if dll and dlm are both zero, the IN16C554A is effectively dis abled, as no baud clock will be generated. table 3 shows the baud rate and divisor value as well as crystal with frequency 1.8432mhz, 3.6864mhz, 7.3728mhz, and 14.7456mhz, respectively. figure 7 shows the crystal clock circuit reference. table 3: baud rates desired baud rate 16x digit divisor 1.8432mhz 3.6864mhz 7.3728mhz 14.7456mhz 50 0900h 1200h 2400h 4800h 75 0600h 0c00h 1800h 3000h 150 0300h 0600h 0c00h 1800h 300 0180h 0300h 0600h 0c00h 600 00c0h 0180h 0300h 0600h 1200 0060h 00c0h 0180h 0300h 1800 0040h 0080h 0100h 0200h 2000 003ah 0074h 00e8h 01d0h 2400 0030h 0060h 00c0h 0180h 3600 0020h 0040h 0080h 0100h 4800 0018h 0030h 0060h 00c0h 7200 0010h 0020h 0040h 0080h 9600 000ch 0018h 0030h 0060h 19.2k 0006h 000ch 0018h 0030h 38.4k 0003h 0006h 000ch 0018h 57.6k 0002h 0004h 0008h 0010h 115.2k 0001h 0002h 0004h 0008h 230.4k D 0001h 0002h 0004h 460.8k D D 0001h 0002h 921.6k D D D 0001h
IN16C554A quadruple uart february 2009 rev 1.01 13 figure 7: baud rate generator block diagram table 4: component values frequency range (mhz) c1 (pf) c2 (pf) r1 ( ? ) r2( ? ) 1.8~8 22 68 220k 470 ~ 1.5k 8~16 33~68 33 ~ 68 220k ~ 2.2m 470 ~ 1.5k 6.3 break and time-out conditions break condition: break condition is occurred when txd signal outputs ?0? and sustains for more than one character. it is occurred if lcr[6] is set to ?1? and delet ed if ?0?. if break condition is occurred when normal data are transmitted on txd, break si gnal is transmitted and internal serial data are also transmitted, but they are not ou tputted to external txd pin. when break condition is deleted, then they are transmitted to txd pin. figure 7 below shows the break condition block diagram. time-out condition: when serial data is received from external uart, characters are stored in rx fifo. when the number of characters in rx fifo reaches the trigger level, interrupt is generated for the cpu to treat characters in rx fifo. but when the number of characters in rx fifo does not reach the trigger le vel and no more data arrives from external device, interrupt is not ge nerated and therefore cpu cannot recognize it. IN16C554A offers time-out function for this situation. time-out function generates an interrupt and reports to cpu when the number of rx fifo is less than trigger level and no more data receives for four character time. time-out interrupt is enabled when ier[2] is set to ?1? and can be verified by isr. c1 sb16c554a crystal external xta l 2 xta l 1 clock r2 xta l 2 optional r1 sb16c554a c2 xta l 1 output clock
IN16C554A quad uart july 2008 rev 0.99 14 7. register descriptions address a[2:0] lcr[7] = 0 lcr[7] = 1 lcr[7:0] bfh 0h thr/rbr dll 1h ier dlm 2h fcr/isr 3h lcr 4h mcr 5h lsr 6h msr 7h spr table 5: internal registers map? continued address a[2:0] register read/write comments registers 0h thr : transmit holding register rbr : receive buffer register write-only read-only lcr[7] = 0 1h ier : interrupt enable register read/write lcr[7] = 0 2h fcr : fifo control register isr : interrupt status register write-only read-only lcr[7] = 0 lcr[7] = 1, lcr bfh 3h lcr : line control register read/write 4h mcr : modem control register read/write lcr[7] = 0 lcr[7] = 1, lcr bfh, lcr[7] = 0 5h lsr : line status register read-only lcr[7] = 0 lcr[7] = 1, lcr bfh 6h msr : modem status register read-only lcr[7] = 0 lcr[7] = 1, lcr bfh 7h spr : scratch pad register read/write lcr[7] = 0 lcr[7] = 1, lcr bfh 0h dll : divisor latch lsb read/write lcr[7] = 1, lcr bfh 1h dlm : divisor latch msb read/write lcr[7] = 1, lcr bfh
IN16C554A quadruple uart february 2009 rev 1.01 15 table 6: internal registers description addr. a[2:0] reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0 registers 0h thr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0h rbr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1h ier 0 0 0 0 modem status interrupt enable receive line status interrupt enable thr empty interrupt enable receive data available interrupt enable 2h isr fifos enabled fifos enabled 0 0 interrupt priority bit 3 interrupt priority bit 2 interrupt priority bit 1 interrupt priority bit 0 2h fcr rx trigger level (msb) rx trigger level (lsb) reserved reserved dma mode select tx fifo reset rx fifo reset fifo enable 3h lcr divisor enable set tx brake set parity parity type select parity enable stop bits word length bit 1 word length bit 0 4h mcr 0 0 autoflow control enable 0/loop back out/ intx enable reserved rts# dtr# 5h lsr rx fifo data error thr & tsr empty thr empty receive break framing error parity error overrun error receive data ready 6h msr dcd# ri# dsr# cts# ? dcd# ? ri# ? dsr# ? cts# 7h scr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0h dll bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1h dlm bit 15 bit 14 bit 13 bi t 12 bit 11 bit 10 bit 9 bit 8 7.1 interrupt enable register (ier) ier enables each of the four types of in terrupt, namely receive data ready, transmit empty, line status, modem status. all inte rrupts are disabled if bit[7:0] are cleared. interrupt is enabled by setting appropriate bits. table 9 shows ier bit settings.
IN16C554A quad uart july 2008 rev 0.99 16 table 7: interrupt enab le register description bit symbol description 7:4 ier[7:4] these four bits of the ier are cleared 3 ier[3] modem status interrupt enable 0 : disable the modem status register interrupt (default). 1: enable the modem status register interrupt. 2 ier[2] receive line status interrupt enable 0 : disable the receive line status interrupt (default). 1: enable the receive line status interrupt. 1 ier[1] transmit holding register interrupt enable 0 : disable the thr interrupt (default). 1 : enable the thr interrupt. 0 ier[0] receive buffer register interrupt enable 0 : disable the rbr interrupt (default). 1 : enable the rbr interrupt. 7.2 interrupt status register (isr) the uart provides multiple levels of prioritized interrupts to minimize software work load. isr provides the source of interrupt in a prioritized manner. table 10 shows isr[7:0] bit settings. table 8: interrupt status register description bit symbol description 7:6 isr[7:6] isr[7:6] are set when fcr[0]=1 mirror the content of fcr[0]. table 8: interrupt status register description? continued bit interrupt priority li st and reset functions 5:0 priority interrupt type interrupt source interrupt reset control 00 _ 0001 D none none D 00 _ 0110 1 receiver line status oe, pe, fe, bi reading the lsr. 00 _ 0100 2 receive data available receiver data available, reaches trigger level. reading the rbr or fifo falls below trigger level. 00 _ 1100 2 character timeout indi- cation at least one data is in rx fifo and there are no more data in fifo during four character time. reading the rbr. 00 _ 0010 3 transmit holding register empty when thr is empty or tx fifo passes above trigger level (fifo enable). reading the isr or write data on thr. 00 _ 0000 4 modem status cts#, dsr#, dcd#, ri# reading the msr.
IN16C554A quadruple uart february 2009 rev 1.01 17 7.3 fifo control register (fcr) fcr is used for enabling the fifos, clearing the fifos, setting transmit/receive fifo trigger level, and selecting the dma modes. table 11 shows fcr bit settings. table 9: fifo control register description bit symbol description 7:6 fcr[7:6] rx fifo trigger level select 00 : 1 characters (default) 01 : 4 characters 10 : 8 characters 11 : 14 characters 5:4 fcr[5:4] fcr[ 5:4] are reserved 3 fcr[3] dma mode select 0 : set dma mode 0 (default) 1 : set dma mode 1 2 fcr[2] tx fifo reset 0 : no tx fifo reset (default) 1 : reset tx fifo pointers and tx fifo level counter logic. this bit will return to ?0? after resetting fifo. 1 fcr[1] rx fifo reset 0 : no rx fifo reset (default) 1 : reset rx fifo pointers and rx fifo level counter logic. this bit will return to ?0? after resetting fifo. 0 fcr[0] fifo enable 0 : disable the tx and rx fifo (default). 1 : enable the tx and rx fifo 7.4 line control register (lcr) lcr controls the asynchronous data communi cation format. the word length, the number of stop bits, and the parity type are selected by writing the appropriat e bits to the lcr. table 12 shows lcr bit settings. table 10: line control register description bit symbol description 7 lcr[7] divisor latch enable. 0 : disable the divisor latch (default). 1 : enable the divisor latch. 6 lcr[6] break enable. 0 : no tx break condition output (default). 1 : forces txd output to ?0?, for alerting the communication terminal to a line break condition. 5 lcr[5] set stick parity.
IN16C554A quad uart july 2008 rev 0.99 18 lcr[5:3] = xx0 : no parity is selected. lcr[5:3] = 0x1 : stick parity disabled. (default) lcr[5:3] = 101 : stick parity is forced to ?1?. lcr[5:3] = 111 : stick parity is forced to ?0?. 4 lcr[4] parity type select. lcr[5:3] =001 : odd parity is selected. lcr[5:3] =011 : even parity is selected. 3 lcr[3] parity enabled. 0 : no parity (default). 1 : a parity bit is generated during the transmission and the receiver checks for receive parity. 2 lcr[2] number of stop bits. lcr[2:0] = 0xx : 1 stop bit (word length = 5, 6, 7, 8). lcr[2:0] = 100 : 1.5 stop bits (word length = 5). lcr[2:0] = 11x or 1x1 : 2 stop bits (word length = 6, 7. 8). 1:0 lcr[1:0] word length bits. 00 : 5 bits (default). 01 : 6 bits. 10 : 7 bits. 11 : 8 bits. 7.5 modem control register (mcr) mcr controls the interface with the modem , data set, or peripheral device that is emulating the modem. table 13 shows mcr bit settings. table 11: modem control register description bit symbol description 7:6 mcr [7:6] these two bits are always cleared 5 mcr[5] autoflow control enable. 0 : auto-rts and auto-cts disabled 1 : if mcr[1]=1, auto-rts and auto-cts enabled (autoflow control enabled) if mcr[1]=1, auto-cts only enabled. 4 mcr[4] internal loop back enable. 0 : disable loop back mode (default). 1 : enable internal loop back m ode. in this mode the mcr[3:0] signals are looped back into msr[7:4] and txd output is looped back to rxd input internally. 3 mcr[3] out/interrupt output enable. 0 : intx outputs disabled (default). during loop back mode, out2 output ?0? and it controls msr[7] to ?1?. 1 : intx outputs enabled. during loop back mode, out2 output
IN16C554A quadruple uart february 2009 rev 1.01 19 ?1? and it controls msr[7] to ?0?. out is not available as an output pin on the IN16C554A. 2 mcr[2] it has no effect on operation. 1 mcr[1] rts# output. 0 : force rts# output to ?1?. during loop back mode, controls msr[4] to ?1?. 1 : force rts# output to ?0?. during loop back mode, controls msr[4] to ?0?. 0 mcr[0] dtr# output. 0 : force dtr# output to ?1?. during loop back mode, controls msr[5] to ?1?. 1 : force dtr# output to ?0?. during loop back mode, controls msr[5] to ?0?. 7.6 line status register (lsr) lsr provides the status of data transfers between the ua rt and the cpu. when lsr is read, lsr[4:2] reflect the error bits (bi, fe , pe) of the character at the top of the rx fifo. the errors in a character are identified by reading lsr and then reading rbr. reading lsr does not cause an increment of the rx fifo read pointer. the rx fifo read pointer is incremented by reading the rbr. table 14 shows lsr bit settings. table 12: line status register description bit symbol description 7 lsr[7] rx fifo data error indicator. 0 : no rx fifo error (default). 1 : at least one parity error, framing error, or break indication is in the rx fifo. this bit is cleared when there is no more error in any of characters in the rx fifo. 6 lsr[6] thr and tsr empty indicator. 0 : thr or tsr is not empty. 1 : thr and tsr are empty. 5 lsr[5] thr empty indicator. 0 : thr is not empty. 1 : thr is empty. it indicates that the uart is ready to accept a new character for transmission. in addition, it uses the uart to gener- ate an interrupt to the cpu when the thr empty interrupt enable is set to ?1?. 4 lsr[4] break interrupt indicator. 0 : no break condition (default). 1 : the receiver received a break signal (rxd was ?0? for at least one character frame time). in fifo mode, only one character is loaded
IN16C554A quad uart july 2008 rev 0.99 20 into the rx fifo. 3 lsr[3] framing error indicator. 0 : no framing error (default). 1 : framing error. it indicates that the received character did not have a valid stop bit. 2 lsr[2] parity error indicator. 0 : no parity error (default). 1 : parity error. it indicates that the receive character did not have the correct even or odd parity, as selected by the lcr[4] 1 lsr[1] overrun error indicator. 0 : no overrun error (default). 1 : overrun error. it indicates that the character in the rbr or rx fifo was not read by the cpu, ther eby ignored the receiving character. 0 lsr[0] receive data ready indicator. 0 : no character in the rbr or rx fifo. 1 : at least one character in the rbr or rx fifo. 7.7 modem status register (msr) msr provides the current stat us of control signals from modem or auxiliary devices. msr[3:0] are set to ?1? when input from modem changes and cleared to ?0? as soon as cpu reads msr. table 15 shows msr bit settings. table 13: modem status register description bit symbol description 7 msr[7] dcd input status. complement of data carrier detect (dcd#) input. in loop back mode this bit is equivalent to out2 in the mcr. 6 msr[6] ri input status. complement of ring indicator (ri#) input. in loop back mode this bit is equivalent to out1 in the mcr. 5 msr[5] dsr input status. complement of data set ready (dsr#) input. in loop back mode this bit is equivalent to dtr in the mcr. 4 msr[4] cts input status. complement of clear to send (cts#) input. in loop back mode this bit is equivalent to rts in the mcr. 3 msr[3] ? dcd input status. 0 : no change on cd# input (default). 1 : indicates that the dcd# input has changed state.
IN16C554A quadruple uart february 2009 rev 1.01 21 2 msr[2] ? ri input status. 0 : no change on ri# input (default). 1 : indicates that the ri# input has changed state from ?0? to ?1?. 1 msr[1] ? dsr input status. 0 : no change on dsr# input (deault). 1 : indicates that the ds r# input has changed state. 0 msr[0] ? cts input status. 0 : no change on cts# input (deault). 1 : indicates that the ct s# input has changed state. 7.8 scratch pad register (spr) this 8-bit read/write register does not control the uart in anyway. it is intended as a scratch pad register to be used by the programmer to hold data temporarily. 7.9 divisor latches (dll, dlh) two 8-bit registers which store the 16-bit di visor for generation of the clock in baud rate generator. dlh stores the most significant pa rt of the divisor, and dll stores the least significant part of the divisor. div isor of zero is not recommended. note that dll and dlh can only be written to before sleep mode is enabled, i.e., before ier[4] is set. chapter 6.2 describes the details of divisor latches. table 14: IN16C554A reset conditions registers reset state rbr [7:0] = ?xxxx_xxxx? ier [7:0] = ?0000_0000? fcr [7:0] = ?0000_0000? isr [7:0] = ?0000_0001? lcr [7:0] = ?0000_0000? mcr [7:0] = ?0000_0000? lsr [7:0] = ?0110_0000? msr [7:4] = ?0000? [3:0] = logic levels of the inputs inverted spr [7:0] = ?0000_0000? dll [7:0] = ?1111_1111? dlm [7:0] = ?1111_1111? output signals reset state txd, rts#, dtr# logic 1 txrdy# logic 0 rxrdy# logic 1 int tri-state condition = intsel is open or low state logic 0 = intsel is high state
IN16C554A quad uart july 2008 rev 0.99 22 8. programmer?s guide the base set of registers that is used during high-speed data transfer has a straightforward access method. the extended function registers require special access bits to be decoded along with the address lines. the following guide will help with programming these registers. no te that the descriptions below are for individual register access. some streamlining through interleaving can be obtained when programming all the registers. table 15: register programming guide command action set baud rate to value1, value2 read lcr, save in temp set lcr to 80h set dll to value1 set dlm to value2 set lcr to temp read flow control status read lcr, save in temp1 read mcr, save in temp2 set lcr to (?0111_1111? and temp1) set mcr to (?0100_0000? or temp2) read fsr, save in temp3 pass temp3 back to host set mcr to temp2 set lcr to temp1 read tx fifo / rx fifo count value read lcr, save in temp1 read mcr, save in temp2 set lcr to (?0111_1111? and temp1) set mcr to (?0100_0000? or temp2) read tcr, save in temp3 read rcr, save in temp4 pass temp3 back to host pass temp4 back to host set mcr to temp2 set lcr to temp1
IN16C554A quadruple uart february 2009 rev 1.01 23 9. electrical characteristics absolute maximum ratings symbol parameter conditions min max unit v cc supply voltage 3.6 v v i input voltage 0.5 5.5 v v o output voltage gnd + 0.1 v cc ? 0.1 v t amb operating ambient temperature in free-air 2 0 +85 t stg storage temperature 60 +150 dc electrical characteristics symbol parameter conditions 3.3v unit min nom max v cc supply voltage 2.7 3.3 3.6 v v i input voltage 0 v cc v v ih high-level input voltage v cc 0.7 5.5 v v il low-level input voltage 0 v cc 0.3 v v o output voltage 0 v cc v v oh high-level output voltage ioh = 8ma 2.4 v v ol low-level output voltage iol = 8ma 0.4 v c i input capacitance 9 pf oscillator/clock speed 85 mhz clock duty cycle 50 % i cc supply current f=14.7456mhz 37.8 ma i ccsleep sleep current f=14.7456mhz 2.5 ma
IN16C554A quad uart july 2008 rev 0.99 24 symbol parameter min max unit t rd pulse duration, ior# low 24 ns t csr set up time, csx# valid before ior# low ? 10 ns t ar set up time, a2~a0 valid before ior# low ? 10 ns t ra hold time, a2~a0 vali d after ior# high ? 2 ns t rcs hold time, csx# valid after ior# high ? 0 ns t frc delay time, t ar +t rd +t rc ? 54 ns t rc delay time, ior# high to ior# or iow# low 20 ns t wr pulse duration, iow# 24 ns t csw setup time, csx# valid before iow# 10 ns t aw setup time, a2~a0 valid before iow# 10 ns t ds setup time, d7~d0 valid before iow# 15 ns t wa hold time, a2~a0 valid after iow# 2 ns t wcs hold time, csx# valid after iow# 2 ns t dh hold time, d7~d0 valid after iow# 5 ns t fwc delay time, t aw +t wr +t wc 54 ns t wc delay time, iow# to iow# or ior# 20 ns t rvd enable time, ior# to d7~d0 valid 24 ns t hz disable time, ior# to d7~d0 released 4 ns t irs delay time, intx to txdx at start 8 24 rclk t sti delay time, txdx at start to intx 8 8 rclk t si delay time, iow# high or low (wr thr) to intx 16 32 rclk t sxa delay time, txdx at start to txrdy# 8 rclk t hr propagation delay time, iow#(wr thr) to intx 12 ns t ir propagation delay time, ior#(rd iir) to intx 12 ns t wxi propagation delay time, iow#(wr thr) to txrdy# 10 ns t sint delay time, stop bit to intx or stop bit to rxrdy# or read rbr to set interrupt 1 rclk t rint propagation delay time, read rbr/lsr to intx /lsr interrupt 12 ns t rint propagation delay time, ior# rclk to rxrdy# 12 ns t mdo propagation delay time, iow#(wr mcr) to rtsx#, dtrx# 12 ns t sim propagation delay time, modem input ctsx#, dsrx#, and dcdx# to intx 12 ns t rim propagation delay time, ior#(rd msr) to interrupt 3 ns t sim propagation delay time, rix# to intx# 12 ns ? the internal address strobe is always in active state. ? in the fifo mode, td1= xxns (min) between reads of the fifo and the status register.
IN16C554A quadruple uart february 2009 rev 1.01 25 t t ra t ior# t csx# t t t a[2:0] v a lid da ta hz v a lid a ddress d[7:0] rvd rc iow# rd rcs ar t csr t active frc figure 8: read cycle timing fwc wr t dh active t t wa t t d[7:0] t wc t a[2:0] t valid data t valid address csx# aw wcs csw ds iow# ior# figure 9: write cycle timing
IN16C554A quad uart july 2008 rev 0.99 26 hr t irs t t sti si hr txdx t parity t intx ir iow# start ior# start (wr thr) (rd iir) stop(1-2) data(5-8) t figure 10: transmitter timing start stop (wr thr) iow# parity txdx data txrdy# sxa t wxi t by te #1 figure 11: transmitter ready mode 0 timing sxa t txdx txrdy# t stop iow# fifo full start parity wxi data by te #16 (wr thr) figure 12: transmitter ready mode 1 timing
IN16C554A quadruple uart february 2009 rev 1.01 27 (fifo at or above t (rd lsr) sint rint ior# (rd rbr) lsi interrupt (fcr6, 7 = 0, 0) data(5-8) start intx(trigger ior# level interrupt clock sample rint t rxdx t trigger level) stop (fifo below parity trigger level) figure 13: receiver fifo first byte (sets rbr) timing trigger level clock stop trigger level) sint (rd lsr) t sint t ior# rint (rd rbr) t rint trigger level) t rxdx (fifo at or above sample interrupt top byte of fifo (fifo below read from fifo lsi interrupt previous byte ior# timeout or figure 14: receiver fifo after first byte (after rbr set) timing
IN16C554A quad uart july 2008 rev 0.99 28 rxdx t rxrdy# rint (rd rbr) ior# clock sample sint t stop (first byte) figure 15: receiver ready mode 0 timing sample sint reaches the rxdx t trigger level) t ior# rint rxrdy# clock (first byte that stop (rd rbr) figure 16: receiver ready mode 1 timing sim rtsx#, dtrx# (wr mcr) t t rim t t sim rim t sim t iow# mdo (rd msr) mdo ior# t intx ctsx#, dsrx#, dcdx# rix# figure 17: modem control timing
IN16C554A quadruple uart february 2009 rev 1.01 29 10. package outline 80-pin tqfp: thin plastic quad flat package; body 12 12 1.0 mm 0,17 0,27 14,00 12,00 9,50 1,20 max 1,05 0,95 0,50 0,10 1.00 0 - 7 0,75 0,45 note : 1. all dimensions are in millimeters. 2. falls within ansi y14.5-1982
IN16C554A quad uart july 2008 rev 0.99 30 68-pin plcc: plastic leaded chip carrier 0.956 (24,282) 0.956 (24,282) 0.02 (0,51) min 0.18 (4,57) max 0.120 (3,05) 0.090 (2,29) 0.469 (11,913) 0.469 (11,913) 0.021 (0,53) 0.013 (0,33) 0.032 (0.081) 0.050 (1,27) 0.026 (0,66) 0.985 (25,019) 0.950 (24,130) 0.985 (25,019) 0.950 (24,130) 0.441 (11,201) 0.441 (11,201) 0.995 (25,273) 0.995 (25,273) note : 1. all dimensions are in inches (millimeters). 2. falls within ansi y14.5-1982
IN16C554A quadruple uart february 2009 rev 1.01 31 64-pin tqfp: thin plastic quad flat package; body 10 10 1.0 mm 10 12 7.5 1.05 max 1.20 max 0.5 0.27 0.17 0.10 0.75 1.00 0 - 7 0.45 note : 1. all dimensions are in inches (millimeters). 2. falls within ansi y14.5-1982

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